I/O Architecture: How the CPU Communicates with the World

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; ==============================================
; Basic I/O Port Operations - x86 Assembly
; ==============================================
 
; Reading from a port (IN instruction)
; -------------------------------------
; IN destination, port
; - destination: AL (byte), AX (word), or EAX (dword)
; - port: immediate (0-255) or DX register (0-65535)
 
; Read byte from port 0x60 (keyboard data)
in al, 0x60           ; Direct port addressing (8-bit port number)
 
; Read byte from port 0x03F8 (COM1 data)
mov dx, 0x3F8         ; Port number in DX (for ports > 255)
in al, dx             ; Indirect port addressing
 
; Read word (16-bit) from port 0x1F0 (IDE data)
mov dx, 0x1F0
in ax, dx             ; Reads from port 0x1F0 and 0x1F1
 
; Read double word (32-bit) from port
mov dx, 0xCFC         ; PCI Configuration Data port
in eax, dx            ; Reads 4 bytes atomically
 
; Writing to a port (OUT instruction)
; ------------------------------------
; OUT port, source
; - port: immediate (0-255) or DX register (0-65535)
; - source: AL (byte), AX (word), or EAX (dword)
 
; Write byte to port 0x20 (PIC command)
mov al, 0x20          ; End-of-interrupt command
out 0x20, al          ; Send to master PIC
 
; Write word to port 0x1F0 (IDE data)
mov dx, 0x1F0
mov ax, 0x1234
out dx, ax            ; Write 16 bits to IDE controller
 
; String I/O Operations
; ----------------------
; For bulk data transfers, string I/O is more efficient
 
; Read 256 words from IDE into memory buffer
mov dx, 0x1F0         ; Source port
mov edi, buffer       ; Destination memory address
mov ecx, 256          ; Number of words to read
rep insw              ; Repeat IN word, store at ES:EDI, increment EDI
 
; Write 256 words from memory buffer to IDE
mov dx, 0x1F0         ; Destination port
mov esi, buffer       ; Source memory address
mov ecx, 256          ; Number of words to write
rep outsw             ; Repeat OUT word from DS:ESI, increment ESI

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/*
 * x86 Task State Segment structure with I/O Permission Bitmap
 * 
 * The TSS is a hardware-defined structure that the CPU uses during
 * task switches and privilege level changes.
 */
 
#include <stdint.h>
 
/* TSS structure for 32-bit protected mode */
struct tss32 {
    uint16_t link;              /* Previous TSS (for hardware task switching) */
    uint16_t reserved0;
    uint32_t esp0;              /* Stack pointer for ring 0 */
    uint16_t ss0;               /* Stack segment for ring 0 */
    uint16_t reserved1;
    uint32_t esp1;              /* Stack pointer for ring 1 */
    uint16_t ss1;               /* Stack segment for ring 1 */
    uint16_t reserved2;
    uint32_t esp2;              /* Stack pointer for ring 2 */
    uint16_t ss2;               /* Stack segment for ring 2 */
    uint16_t reserved3;
    uint32_t cr3;               /* Page directory base */
    uint32_t eip;               /* Instruction pointer */
    uint32_t eflags;            /* Flags register (includes IOPL) */
    uint32_t eax, ecx, edx, ebx;
    uint32_t esp, ebp, esi, edi;
    uint16_t es, reserved4;
    uint16_t cs, reserved5;
    uint16_t ss, reserved6;
    uint16_t ds, reserved7;
    uint16_t fs, reserved8;
    uint16_t gs, reserved9;
    uint16_t ldt;               /* LDT segment selector */
    uint16_t reserved10;
    uint16_t trap;              /* Debug trap on task switch */
    uint16_t io_bitmap_base;    /* Offset to I/O permission bitmap */
    
    /* I/O Permission Bitmap follows (up to 8KB + 1 byte) */
    /* Bit = 0: port access allowed */
    /* Bit = 1: port access denied (causes #GP) */
    uint8_t io_bitmap[8192 + 1]; /* 65536 ports / 8 bits per byte + trailing 0xFF */
} __attribute__((packed));
 
/*
 * Example: Grant access to specific ports
 * 
 * This function modifies the I/O permission bitmap to allow a user-space
 * process to access specific ports (used by specialized applications like
 * parallel port drivers or legacy game compatibility layers).
 */
void grant_port_access(struct tss32 *tss, uint16_t port, uint16_t length) {
    for (uint16_t i = 0; i < length; i++) {
        uint16_t target_port = port + i;
        uint16_t byte_offset = target_port / 8;
        uint8_t bit_offset = target_port % 8;
        
        /* Clear the bit to GRANT access (0 = allowed) */
        tss->io_bitmap[byte_offset] &= ~(1 << bit_offset);
    }
}
 
void revoke_port_access(struct tss32 *tss, uint16_t port, uint16_t length) {
    for (uint16_t i = 0; i < length; i++) {
        uint16_t target_port = port + i;
        uint16_t byte_offset = target_port / 8;
        uint8_t bit_offset = target_port % 8;
        
        /* Set the bit to REVOKE access (1 = denied) */
        tss->io_bitmap[byte_offset] |= (1 << bit_offset);
    }
}
 
/* 
 * Initialize TSS with all I/O ports blocked by default
 * (secure default - principle of least privilege)
 */
void init_tss_io_bitmap(struct tss32 *tss) {
    /* Set all bits to 1 (deny all ports) */
    for (int i = 0; i < sizeof(tss->io_bitmap); i++) {
        tss->io_bitmap[i] = 0xFF;
    }
    
    /* Set io_bitmap_base to point to the bitmap within the TSS */
    tss->io_bitmap_base = offsetof(struct tss32, io_bitmap);
}

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/*
 * 8250/16550 UART Initialization Example
 * 
 * This demonstrates typical port-based device initialization,
 * showing how multiple ports work together to configure a device.
 */
 
#include <stdint.h>
 
/* Port I/O functions (platform-specific implementation) */
static inline void outb(uint16_t port, uint8_t value) {
    __asm__ volatile ("outb %0, %1" : : "a"(value), "Nd"(port));
}
 
static inline uint8_t inb(uint16_t port) {
    uint8_t value;
    __asm__ volatile ("inb %1, %0" : "=a"(value) : "Nd"(port));
    return value;
}
 
/* COM1 base port address */
#define COM1 0x3F8
 
/* Port offsets from base address */
#define UART_DATA       0   /* Data register (RBR/THR) */
#define UART_IER        1   /* Interrupt Enable Register */
#define UART_IIR_FCR    2   /* Interrupt ID / FIFO Control */
#define UART_LCR        3   /* Line Control Register */
#define UART_MCR        4   /* Modem Control Register */
#define UART_LSR        5   /* Line Status Register */
#define UART_MSR        6   /* Modem Status Register */
#define UART_SCRATCH    7   /* Scratch register */
 
/* Divisor Latch registers (when DLAB=1) */
#define UART_DLL        0   /* Divisor Latch Low */
#define UART_DLH        1   /* Divisor Latch High */
 
/* Line Control Register bits */
#define LCR_DLAB        0x80   /* Divisor Latch Access Bit */
#define LCR_8N1         0x03   /* 8 data bits, no parity, 1 stop bit */
 
/* Line Status Register bits */
#define LSR_DR          0x01   /* Data Ready */
#define LSR_THRE        0x20   /* Transmit Holding Register Empty */
 
/* FIFO Control Register bits */
#define FCR_ENABLE      0x01   /* Enable FIFOs */
#define FCR_CLEAR_RX    0x02   /* Clear receive FIFO */
#define FCR_CLEAR_TX    0x04   /* Clear transmit FIFO */
#define FCR_TRIGGER_14  0xC0   /* 14-byte trigger level */
 
/* Modem Control Register bits */
#define MCR_DTR         0x01   /* Data Terminal Ready */
#define MCR_RTS         0x02   /* Request To Send */
#define MCR_OUT2        0x08   /* Enable IRQ line */
 
/*
 * Initialize COM1 serial port for 115200 baud, 8N1
 * 
 * This function demonstrates the choreography of port accesses
 * required to configure a hardware device.
 */
int init_serial(void) {
    uint16_t base = COM1;
    
    /* Step 1: Disable all interrupts during initialization */
    outb(base + UART_IER, 0x00);
    
    /* Step 2: Set baud rate divisor */
    /* Divisor = 115200 / desired_baud_rate */
    /* For 115200 baud: divisor = 1 */
    outb(base + UART_LCR, LCR_DLAB);        /* Set DLAB to access divisor */
    outb(base + UART_DLL, 0x01);            /* Low byte of divisor */
    outb(base + UART_DLH, 0x00);            /* High byte of divisor */
    
    /* Step 3: Configure line protocol (8N1) and clear DLAB */
    outb(base + UART_LCR, LCR_8N1);         /* 8 bits, no parity, 1 stop bit */
    
    /* Step 4: Enable and configure FIFOs */
    outb(base + UART_IIR_FCR, FCR_ENABLE | FCR_CLEAR_RX | FCR_CLEAR_TX | FCR_TRIGGER_14);
    
    /* Step 5: Configure modem control */
    outb(base + UART_MCR, MCR_DTR | MCR_RTS | MCR_OUT2);
    
    /* Step 6: Verify chip exists with loopback test */
    outb(base + UART_MCR, 0x1E);           /* Enable loopback mode */
    outb(base + UART_DATA, 0xAE);          /* Send test byte */
    if (inb(base + UART_DATA) != 0xAE) {
        return -1;  /* Hardware not responding */
    }
    
    /* Step 7: Restore normal operation mode */
    outb(base + UART_MCR, MCR_DTR | MCR_RTS | MCR_OUT2);
    
    return 0;
}
 
/* Send a single character */
void serial_putc(char c) {
    /* Wait until transmit buffer is empty */
    while ((inb(COM1 + UART_LSR) & LSR_THRE) == 0) {
        /* Busy wait - in production, use interrupts or DMA */
    }
    outb(COM1 + UART_DATA, c);
}
 
/* Receive a single character (blocking) */
char serial_getc(void) {
    /* Wait until data is available */
    while ((inb(COM1 + UART_LSR) & LSR_DR) == 0) {
        /* Busy wait */
    }
    return inb(COM1 + UART_DATA);
}

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/*
 * PCI Configuration Space Access via I/O Ports
 * 
 * This demonstrates how a small number of I/O ports (0xCF8, 0xCFC)
 * provide access to the entire PCI device configuration space.
 */
 
#include <stdint.h>
 
#define PCI_CONFIG_ADDR  0xCF8  /* Configuration Address Port */
#define PCI_CONFIG_DATA  0xCFC  /* Configuration Data Port */
 
/* Build PCI configuration address */
#define PCI_ADDR(bus, dev, func, offset) \
    (0x80000000 | ((bus) << 16) | ((dev) << 11) | ((func) << 8) | ((offset) & 0xFC))
 
/* Port I/O functions */
static inline void outl(uint16_t port, uint32_t value) {
    __asm__ volatile ("outl %0, %1" : : "a"(value), "Nd"(port));
}
 
static inline uint32_t inl(uint16_t port) {
    uint32_t value;
    __asm__ volatile ("inl %1, %0" : "=a"(value) : "Nd"(port));
    return value;
}
 
/*
 * Read 32-bit value from PCI configuration space
 */
uint32_t pci_config_read(uint8_t bus, uint8_t device, uint8_t func, uint8_t offset) {
    /* Build and write the configuration address */
    uint32_t address = PCI_ADDR(bus, device, func, offset);
    outl(PCI_CONFIG_ADDR, address);
    
    /* Read the data */
    return inl(PCI_CONFIG_DATA);
}
 
/*
 * Write 32-bit value to PCI configuration space
 */
void pci_config_write(uint8_t bus, uint8_t device, uint8_t func, 
                       uint8_t offset, uint32_t value) {
    uint32_t address = PCI_ADDR(bus, device, func, offset);
    outl(PCI_CONFIG_ADDR, address);
    outl(PCI_CONFIG_DATA, value);
}
 
/* Standard PCI configuration header offsets */
#define PCI_VENDOR_ID       0x00
#define PCI_DEVICE_ID       0x02
#define PCI_COMMAND         0x04
#define PCI_STATUS          0x06
#define PCI_CLASS_CODE      0x08
#define PCI_HEADER_TYPE     0x0E
#define PCI_BAR0            0x10
#define PCI_BAR1            0x14
#define PCI_BAR2            0x18
#define PCI_BAR3            0x1C
#define PCI_BAR4            0x20
#define PCI_BAR5            0x24
 
/*
 * Enumerate all PCI devices on the system
 * 
 * This scans the entire PCI bus space looking for valid devices
 * and reports their vendor ID, device ID, and resource assignments.
 */
void pci_enumerate(void) {
    for (uint16_t bus = 0; bus < 256; bus++) {
        for (uint8_t device = 0; device < 32; device++) {
            for (uint8_t func = 0; func < 8; func++) {
                uint32_t reg0 = pci_config_read(bus, device, func, PCI_VENDOR_ID);
                uint16_t vendor_id = reg0 & 0xFFFF;
                
                /* Vendor ID 0xFFFF indicates no device present */
                if (vendor_id == 0xFFFF) {
                    if (func == 0) break;  /* No device, skip remaining functions */
                    continue;
                }
                
                uint16_t device_id = (reg0 >> 16) & 0xFFFF;
                uint32_t class_reg = pci_config_read(bus, device, func, PCI_CLASS_CODE);
                uint8_t class_code = (class_reg >> 24) & 0xFF;
                uint8_t subclass = (class_reg >> 16) & 0xFF;
                
                /* Example: Print device information */
                /* In real code, log or store this information */
                
                /* Read Base Address Registers for I/O port assignments */
                for (int bar = 0; bar < 6; bar++) {
                    uint32_t bar_value = pci_config_read(bus, device, func, 
                                                         PCI_BAR0 + (bar * 4));
                    if (bar_value == 0) continue;
                    
                    if (bar_value & 0x01) {
                        /* I/O port BAR (bit 0 = 1) */
                        uint32_t io_base = bar_value & 0xFFFFFFFC;
                        /* This device uses I/O ports starting at io_base */
                    } else {
                        /* Memory-mapped BAR (bit 0 = 0) */
                        uint32_t mem_base = bar_value & 0xFFFFFFF0;
                        /* This device uses memory starting at mem_base */
                    }
                }
                
                /* Check for multi-function device */
                if (func == 0) {
                    uint32_t header = pci_config_read(bus, device, func, PCI_HEADER_TYPE);
                    if ((header & 0x80) == 0) {
                        break;  /* Single-function device */
                    }
                }
            }
        }
    }
}